Merry Christmas everyone. I was wondering if anybody could spare a bit of brain power to see if they can come up with a solution to a little challenge I have set myself.
I am interested if the Picaxe is fast enough to generate a DCC model train bitstream. I've copied the DCC standard to the bottom of this post, but to summarise a logical 1 is made of a +5v pulse for 55-61us and a 0v pulse for the same time. A logical 0 has timings that can be anywhere from double this to up to about 10ms.
I have read the previous threads on the forum about doing this but as far as I could see nobody actually got as far as doing tests connected to a scope. The 0's are no problem and are well within picaxe speeds, my experiments with the 1's are close but come in a few us outside of the spec.
My intention is to calculate the bytes and checksum to be sent and store each bit in the scratchpad. Then whiz through the scratchpad banging out the bits in the right timings. To test the concept I am first trying to generate a simple pulse of a logical 1.
With a 20x2 running at 64mhz I have tried the following (scope connected to b.7):-
Pulsout method
ptr=0
@ptrinc=85
@ptrinc=0
@ptrinc=85
@ptrinc=0
ptr=0
pulsout b.7,@ptrinc
pulsout b.6,@ptrinc
pulsout b.7,@ptrinc
pulsout b.6,@ptrinc
This gave me a +5v pulse for about 55us, but the 0v pulse width was near 80us. This seems to be caused by overheads in the pair of pulsout commands.
Toggle method
ptr=0
@ptrinc=0
@ptrinc=0
ptr=0
toggle b.7
pauseus @ptrinc
toggle b.7
pauseus @ptrinc
toggle b.7
This gives me about 65us on both parts of the pulse, which is just slightly too slow even with the pauseus command set to 0. Again I am guessing the overhead of the pauseus command is causing the problem as with just the toggles I get about 30us pulses.
The fact that I am only about 4us out indicates to me that this must just be in the bounds of being doable on a picaxe and would seem like a good project to be able to do with a picaxe as well.
Is there is a better way of doing this at 64mhz? Or do I need to consider one of the following:-
1. Get a 28x2 and trying clocking it up to 80mhz (or more). This should hopefully reduce the overhead enough that I can use the pauseus command to fine tune the exact pause.
2. String a load shift registers together, slowly clock the bits in (a 0 would just take up 2 bits in the register) and then use pwm to clock them out at the right speed. I might have a problem knowing when to stop shifting though???
3. Give up ;-)
DCC bistream standard
In a "1" bit, the first and last part of a bit shall have the same duration, and that duration shall nominally be
58 microseconds2, giving the bit a total duration of 116 microseconds. Digital Command Station
components shall transmit "1" bits with the first and last parts each having a duration of between 55 and 61
microseconds. A Digital Decoder must accept bits whose first and last parts have a duration of between 52
and 64 microseconds, as a valid bit with the value of "1".
In a "0" bit, the duration of the first and last parts of each transition shall nominally be greater than or
equal to 100 microseconds. To keep the DC component of the total signal at zero as with the "1" bits, the
first and last part of the "0" bit are normally equal to one another. Digital Command Station components
shall transmit "0" bits with each part of the bit having a duration of between 95 and 9900 microseconds
with the total bit duration of the "0" bit not exceeding 12000 microseconds. A Digital Decoder must accept
bits whose first or last parts have a duration of between 90 and 10000 microseconds as a valid bit with the
value of "0". Figure 1 provides an example of bits encoded using this technique.
I am interested if the Picaxe is fast enough to generate a DCC model train bitstream. I've copied the DCC standard to the bottom of this post, but to summarise a logical 1 is made of a +5v pulse for 55-61us and a 0v pulse for the same time. A logical 0 has timings that can be anywhere from double this to up to about 10ms.
I have read the previous threads on the forum about doing this but as far as I could see nobody actually got as far as doing tests connected to a scope. The 0's are no problem and are well within picaxe speeds, my experiments with the 1's are close but come in a few us outside of the spec.
My intention is to calculate the bytes and checksum to be sent and store each bit in the scratchpad. Then whiz through the scratchpad banging out the bits in the right timings. To test the concept I am first trying to generate a simple pulse of a logical 1.
With a 20x2 running at 64mhz I have tried the following (scope connected to b.7):-
Pulsout method
ptr=0
@ptrinc=85
@ptrinc=0
@ptrinc=85
@ptrinc=0
ptr=0
pulsout b.7,@ptrinc
pulsout b.6,@ptrinc
pulsout b.7,@ptrinc
pulsout b.6,@ptrinc
This gave me a +5v pulse for about 55us, but the 0v pulse width was near 80us. This seems to be caused by overheads in the pair of pulsout commands.
Toggle method
ptr=0
@ptrinc=0
@ptrinc=0
ptr=0
toggle b.7
pauseus @ptrinc
toggle b.7
pauseus @ptrinc
toggle b.7
This gives me about 65us on both parts of the pulse, which is just slightly too slow even with the pauseus command set to 0. Again I am guessing the overhead of the pauseus command is causing the problem as with just the toggles I get about 30us pulses.
The fact that I am only about 4us out indicates to me that this must just be in the bounds of being doable on a picaxe and would seem like a good project to be able to do with a picaxe as well.
Is there is a better way of doing this at 64mhz? Or do I need to consider one of the following:-
1. Get a 28x2 and trying clocking it up to 80mhz (or more). This should hopefully reduce the overhead enough that I can use the pauseus command to fine tune the exact pause.
2. String a load shift registers together, slowly clock the bits in (a 0 would just take up 2 bits in the register) and then use pwm to clock them out at the right speed. I might have a problem knowing when to stop shifting though???
3. Give up ;-)
DCC bistream standard
In a "1" bit, the first and last part of a bit shall have the same duration, and that duration shall nominally be
58 microseconds2, giving the bit a total duration of 116 microseconds. Digital Command Station
components shall transmit "1" bits with the first and last parts each having a duration of between 55 and 61
microseconds. A Digital Decoder must accept bits whose first and last parts have a duration of between 52
and 64 microseconds, as a valid bit with the value of "1".
In a "0" bit, the duration of the first and last parts of each transition shall nominally be greater than or
equal to 100 microseconds. To keep the DC component of the total signal at zero as with the "1" bits, the
first and last part of the "0" bit are normally equal to one another. Digital Command Station components
shall transmit "0" bits with each part of the bit having a duration of between 95 and 9900 microseconds
with the total bit duration of the "0" bit not exceeding 12000 microseconds. A Digital Decoder must accept
bits whose first or last parts have a duration of between 90 and 10000 microseconds as a valid bit with the
value of "0". Figure 1 provides an example of bits encoded using this technique.