Help needed understanding I2C related info in datasheet

[Mad Professor]

Good day all.

I am soon to be starting a new project, and I am looking for some help and advice before I get in to deep.

I have a 36v e-bike, and the battery pack has a ApolloGroup LT-013SF BMS, and this is based on the 02Micro OZ890 chip.

The 02Micro OZ890 chip has an i2c interface where the parameters of the BMS can be viewed or adjusted.

I just want to be able to monitor and view each of the cells voltages in real time, via an LCD or OLED display.

But at this point in time I just wish to be able to pull each of the cells data, and push the data out over serial, so that I can just view the data via windows serial console monitor.

From reading the 02Micro OZ890 datasheet all the real time data is held in the Operation Registers Map, (Page 65 of Datasheet).

Now this is where I am stuck, I don't yet understand how to use the details of the Operation Registers Map, so that I can call the needed data for use with each of the battery cells.

If someone has the free time, can someone please try and explain it to me?

Thanks for your time.

Best Regards.

 

[westaust55]

From an initial scan of the datasheet, there are some things to be determined before you can successfully communicate with the e-bike battery chip. How much of this is already documented in the e-bike manuals or schematics?


The OZ890 chip only supports a typical clock frequency of 100 kHz (page 10) suggesting the bus speed parameter must be I2CSLOW but on page 17 the max clock speed is 400 kHz suggesting I2CFAST is acceptable.

Recommend start with I2CSLOW first..


From page 33 for Sleep mode:
Because OZ890 needs some time when it first wakes up from Sleep Mode, if it is waken up by I2C access, it will send out "nak" to respond to the first I2C access, so the first I2C access is likely to fail. Host software needs to re-send the I2C command after getting the "nak".


Based upon the OZ890 datasheet page 40 you need to identify whether the chip is configured for 2-wire i2c or 4-wire i2c (PBUS) comms. That is set by two pins BSEL1, BSEL0
(Pin30, Pin31 respectively).


You need to ascertain whether PEC mode is enabled in which case CRC checking is used. (Datasheet page 40)
If you need to imliment CRC chekcing and calculations then you need extra routines. I have previously written some for 1-Wire networks (posted on this forum) and I recall others have written some CRC code as well.


From datasheet page 56:
EEPROM Register 30h – I2C Address Configure and SC Release Control Register
Bit3 – Bit0 (I2CADDR3 – I2CADDR0): Configure the I2C address as 60h + 2*N (N: 0~15).

The timing diagram at the bottom of page 40 indicates how to write data to a register.
The timing diagram at the top of page 41 gives the sequence to read data from a register.

 

[Technical]

Assuming i2c address register is at 0, the 8 bit slave address is $60

So to read adc of cell8 (address $40 and $41)

hi2csetup, hi2cmaster, $60, i2cbyte, i2cslow
readi2c $40, (b0,b1)

Now shuffle the bits around:

b2 = b1 * 32 and %11100000 'get 3 bits in top 3 of b2
b0 = b0/8 or b2 'correct position of the 5 bits already in b0 and merge with those top 3 bits
b1 = b1 / 8 'shuffle b1 down 3 bits to correct high byte

Now w0 (b1:b0) has your ADC reading

 

[Mad Professor]

Thanks for your replies.

Things are now starting to make more sense to me.

I am going to spend some more time reading and re-reading the datasheet tonight, then I hope to do some testing in the next few days.

Thanks again.