MarkLondon
New Member
There is a logic error in the if and/or then command when mixing "AND" with "OR" in the condition with PICAXE Editor 6.0.8.1
The error occurs with a multiple condition of the form: if condition#1 AND condition#2 OR condition#3 then ....
The pdf manual and on-line language guide does not mention any restriction in mixing "AND" with "OR" in the condition. If using this form of condition you may not get the logical outcome you want.
The error is when condition evaluates ( True AND False OR False ) in the if-then.
The situation is the same whether using bit, byte or word variables.
See the example below (with truth table of other cases at the bottom):
The truth table shows the logic for a|b|c and a&b&c conditions in if-then are OK.
The logic for a&b|c gives different results as described, with if-then being incorrect, and giving a|c.
Adding a 4th variable (d) we if we test: a&b&c|d in the if-then we get: (a&b)|d
Conditions of "OR" followed by "AND" e.g. a|b&c work OK
The error occurs with a multiple condition of the form: if condition#1 AND condition#2 OR condition#3 then ....
The pdf manual and on-line language guide does not mention any restriction in mixing "AND" with "OR" in the condition. If using this form of condition you may not get the logical outcome you want.
The error is when condition evaluates ( True AND False OR False ) in the if-then.
The situation is the same whether using bit, byte or word variables.
See the example below (with truth table of other cases at the bottom):
Code:
#picaxe 28X2
'note different results for case#1 and case #2
'evaluating: bit0 and bit1 or bit2
'expected result for 1,0,0, working left to right: 1 and 0 or 0 => (1 and 0) or 0 => (0 or 0) => 0
bit0=1
bit1=0
bit2=0
'case #1: evaluate logic outside if-then ' evaluates -> 0 ,correct
Sertxd ("case #1=")
bit3 = bit0 And bit1 Or bit2
If bit3=1 Then
Sertxd ("1")
Else
Sertxd("0")
End if
'case #2: evaluate logic inside if-then 'evaluates -> 1, error
Sertxd ("case #2=")
If bit0=1 And bit1=1 Or bit2=1 Then
Sertxd ("1")
Else
Sertxd("0")
End if
#rem
This is a truth table for all patterns tested:
bits (0,1,2) Logic case#1 case#2: is not if-then
a b c | & a&b|c_#1 a&b|c_#2
0 0 0 0 0 0 0
1 0 0 1 0 1 (!) 0
0 1 0 1 0 0 0
1 1 0 1 0 1 1
0 0 1 1 0 1 1
1 0 1 1 0 1 1
0 1 1 1 0 1 1
1 1 1 1 1 1 1
result OK OK Error OK
#endremThe logic for a&b|c gives different results as described, with if-then being incorrect, and giving a|c.
Adding a 4th variable (d) we if we test: a&b&c|d in the if-then we get: (a&b)|d
Conditions of "OR" followed by "AND" e.g. a|b&c work OK
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