Build a 14M based Logic Probe

0)  <= ~ 0.10 V    then effectively at 0V rail  
1) <= ~ 0.15*Vdd and Vdd = 3 V then a TTL low state, or 
             if <= 0.8V at 4.5/5V then TTL low state (plus ST plus CMOS)
2) <= ~ 0.20*Vdd  then a Schmitt Trigger low state plus CMOS low state
3) <= ~ 0.266*Vdd then only a CMOS low state
4) > state (3) and < state (5) is logic indeterminate or tri-stated/high impedance  
5)  > ~ 0.25*Vdd+0.8V and Vdd = 3 V then TTL high state or
            if > 2.0 V at 4.5/5V then TTL high State
6)  > ~ 0.733*Vdd then also a CMOS high state (CMOS + TTL)  
7)  > ~ 0.8*Vdd   then also a Schmitt Trigger High plus TTL high plus CMOS high
8)  > Vdd - 0.2V then effectively at Vdd rail

;===============================================================================
; Program using a PICAXE 14M and 7-Segment display as a logic level probe
;
;
;                                    ____  ____
;  +Vcc ----------------------  +V -|    \/    |- 0V
;                                   |          |
;                                   |          |
;     Std Program cct here - SerIn -|          |- SerOut
;                                   |          |
;                                   |          |
;  +V - 1k0-+----- Vref on ADC4 In -|  PICAXE  |- LED 'A' 
;           |                       |          |
;         | |                       |          |
;          ---          Unused In3 -|   14M    |- LED 'B'
;          / \ 2.4V Zener           |          |
;          ---                      |          |
;           |           LED 'G' C5 -|          |- LED 'C'      
;          0V                       |          |
;                                   |          |
;                       LED 'F' C4 -|          |- LED 'D'
;  +V - 10M-+                       |          |
;           |                       |          |
; Probe-----+---------------ADC0In -|          |- LED 'E'
;           |                       +----------+
;          4M7 
;           |
;          0V
;
;
;

;
;
;  PICAXE pins via 620 Ohm resisitors to all 7-Seg display segments. dp via 1k0 Ohm to Vdd as 'On' indicator.
;
;  Programming circuit resistors not shown for clarity.
;
;  Potential divider using 10M and 4M7 resistors holds the probe pin in an indeterminate state when no signal present.
;
;  1k0 resistor in series with 2.4V zener diode as simple ref voltage to detect Vdd level (3, 4.5 or 5 Volts)
;
; Definition of (state) if signal at probe is:
; (0) <= ~ 0.10 V    then effectively at 0V rail  
; (1) <= ~ 0.15*Vdd and Vdd = 3 V then a TTL low state, or if <= 0.8V at 4.5/5V then TTL low state (plus ST plus CMOS)
; (2) <= ~ 0.20*Vdd  then a Schmitt Trigger low state plus CMOS low state
; (3) <= ~ 0.266*Vdd then only a CMOS low state
; (4) > state (3) and < state (5) is logic indeterminate or tri-stated/high impedance  
; (5)  > ~ 0.25*Vdd+0.8V and Vdd = 3 V then TTL high state of if > 2.0 V at 4.5/5V then TTL high State
; (6)  > ~ 0.733*Vdd then also a CMOS high state (CMOS + TTL)  
; (7)  > ~ 0.8*Vdd   then also a Schmitt Trigger High plus TTL high plus CMOS high
; (8)  > Vdd - 0.2V then effectively at Vdd rail  
; (9) If there are pulses are greater than a pre defined frequency (typcally 8 Hz) then the display indicate "P"
;
;
; 7 Segment display images for states 0 to 9
;   (0)    (1)    (2)    (3)    (4)    (5)    (6)    (7)    (8)   (9)
;
;   . .    ._.    ._.    . .    . .    . .    ._.    . .    ._.   ._.
;          | |    | |                         |        |          | | 
;   . .    . .    .-.    .-.    .-.    . .    .-.    . .    . .   .-.
;          | |           |               |      |      |          |
;   .-.    .-.    .-.    .-.    . .    . .    . .    . .    . .   . .
;
;
;
#PICAXE 14M
EEPROM 0, (%00010000, %01111110, %11000110, %10110000, %10000000,%00001000,%11001010, %00001100,%00000010,%11100110)

SYMBOL LED	  = b0    ; Bit code from EEPROM to set the 7-Segment display for current signal logic state
SYMBOL Vref   = b1    ; Reference Voltage read by ADC from 2.4V zener voltage
SYMBOL Logic  = b2    ; Circuit Signal Voltage 
SYMBOL Vss    = b3    ; Supply voltage x 10
SYMBOL State  = b4    ; state for the current signal logic level
SYMBOL Prev   = b5    ; Used to hold a previous logic state
SYMBOL Temp   = b6    ; Temporary variable
SYMBOL Spare1 = b7
SYMBOL Spare2 = b8
SYMBOL Spare3 = b9
SYMBOL Spare4 = b10
SYMBOL Spare5 = b11
SYMBOL PlsChk = w6    ; w6 = b13:b12

SYMBOL PlsDur   = 1000 ; pulse check duration - 1000 = 500ms at 8MHz
SYMBOL Min4pls  = 4   ; minimum number of pulses in the pulse duration before a pulse train is deemed to exist

SYMBOL RefPin   = 4   ; input 0 as ADC for reference voltage
SYMBOL ProbePin = 0   ; input 4 as ADC for the signal being monitored

#TERMINAL 9600
; ===============================================================================
;Initialiseation - here we identify the circuit supply voltage as a reference for
;determination of the various voltage levels
; 
Init:
	
	SETFREQ m8
	PAUSE 1000 ; wait for 1 second for Programming Editor Terminal Window to initialise
	Prev = 9	; set an invalid state so always updates the display on the first pass after power-up.
	READADC RefPin, Vref
	SERTXD (#Vref, "  " )
	Vss = 50
	IF Vref >= 150 THEN
		Vss = 30
	ELSE IF Vref >= 130 THEN
		Vss = 45
	ENDIF
	Prev = Vss /10
	Temp = Vss // 10
	SERTXD (#Prev, ".", #Temp, " Volts.", CR, LF)
; ===============================================================================
; Main program loop to read the signal and determine the logic level.
;
Main:
	READADC ProbePin, Logic	; read the signal voltage level from circuit under test
	
	State = 8						; set as tied to Vdd rail by default,
								; then test if
	IF Logic <= 10  THEN 				; <= ~ 0.1 volts = direct to 0V rail ==> "_"
		State = 0
	ELSEIF Logic <=  40 AND Vss = 30 THEN	; <= 0.15*Vdd with 3 V supply = TTL Low 
		State = 1
	ELSEIF Logic <=  43 AND Vss = 50 THEN	; <= 0.80 V with 5.0 V supply = TTL Low
		State = 1
	ELSEIF Logic <=  47 AND Vss = 45 THEN	; <= 0.80 V with 4.5 V supply = TTL Low
		State = 1
	ELSEIF Logic <=  57 THEN			; <= 0.20*Vdd at any voltage for Schmitt Trigger Low
		State = 2
	ELSEIF Logic <=  70 THEN			; <= 0.266*Vdd at any voltage for CMOS Low
		State = 3
	ELSEIF Logic <=  99 AND Vss = 50 THEN	; <= 2.0V at 5.0 V supply (for min high state) = indeterminate
		State = 4
	ELSEIF Logic <= 108 AND Vss = 45 THEN	; <= 2.0V at 4.5 V supply (for min high state) = indeterminate
		State = 4
	ELSEIF Logic <= 130 AND Vss = 30 THEN	; <= 0.25*Vdd+0.8V at 3V (for min high state) = indeterminate
		State = 4	
	ELSEIF Logic <= 185 THEN			; < = ~0.733*Vdd at any voltage for CMOS High = high for TTL only
		State = 5
	ELSEIF Logic <= 202 THEN			; <= 0.80*Vdd at any voltage = high for TTL and CMOS
		State = 6
	ELSEIF Logic <= 240 THEN			; <= Vdd-0.2V at any voltage = high for Schmitt Trigger, TTL and CMOS 
		State = 7
	ENDIF
	
	COUNT ProbePin, PlsDur, PlsChk
	IF PlsChk > Min4pls THEN
	  State = 9                               ; A pulse train has bee detected 
	ENDIF
	 
	IF State = Prev THEN Main			; return now as no need to update the LED display
	
	READ State, LED
	OUTPINS = LED AND %00111110 			; Set up 7-segment parts A, B, C, D and E
	IF bit6 = 1 THEN
		HIGH PortC 4				; Set up 7-Segment parts F
	ELSE
		LOW  PortC 4
	ENDIF
	IF bit7 = 1 THEN
		HIGH PortC 5				; Set up 7-Segment parts G
	ELSE
		LOW  PortC 5
	ENDIF
	Prev = State
	GOTO Main