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Thread: i2c switching between master and slave

  1. #1
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    Default i2c switching between master and slave

    Hey folks,

    I'm designing an i2c network consisting exclusively of picaxe chips and a 24LC512 EEPROM. At one end, I've got a pair of chips communicating with a PC over serial, one an i2c slave handling serial comms to the PC, and the other an i2c master receiving data from the pc.
    I know that the i2c protocol in theory protects the network from multiple masters transmitting at once. however, does the picaxe system also have this protection, where a master waits for the bus to be free before taking command and sending data?
    If this doesn't work, my other option (much less preferred) is for the master chip to poll each of the chips one at a time to check for updates. How long would this take for, for example, 10 chips to have one bit parsed each?

    Cheers folks

  2. #2
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    The PICAXE does not support multi-master I2C. You would need to have a separate mechanism where each PICAXE could take control of the bus and ensure no other accessed it at the same time.

    It is hard to say how long a complete polling cycle would take. At an I2C bus speed of 100K it may only take half a millisecond for each PICAXE to read a byte of data from the I2C EEPROM but there would be additional time needed to handle the access arbitration. That would depend on what arbitration scheme was used and how optimised that was. I would guess at a few tens of milliseconds.

    Directly polling PICAXE via serial could be quite quick but would again depend on implementation. PICAXE X2 chips can be interrupted and send a reply almost immediately, but M2 chips would have to themselves poll to see if they have been polled to send a reply.

    Added: It's probably best to start with what the entire system is doing, what each chip does, what data needs to be transferred and determine the best options for achieving that rather than try and guess what option best fits what you need to do.
    Last edited by hippy; 14-11-2017 at 13:08.

  3. #3
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    Hi,

    AFAIK, I2C was primarily intended as a Single-Master protocol and that's all the vast majority of applications use (although "extensions" for multiple-Masters may exist). Some Masters even use a Low/High output (not Low/float) to drive the SCL, in place of the normal Wired-Or (resistor pullup).

    So you probably need an additional "Arbitration Bus", which might be just a 3rd Wired-Or link between a pin on each Master (or in non-critical applications perhaps you could get away with using the SDA line). I've never tried it, but for fairly reliable arbitration you should probably first test the Arbitration Bus (perhaps quickly several times) to check that it is free (High) and if so, pull it Low. Then immediately read the pin again (which PICaxe Basic will automatically restore as as input) and then pull it Low again. If the pin read as Low, then another Master had also claimed the bus and the program should release the pin an wait for a (ideally random) period of some milliseconds before trying again.

    Cheers, Alan.

  4. #4
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    A pulled-up ADC line in and something to pull it low via the same value resistor is probably a good mechanism. Reads high (255) when available, about half (128) when one has it, below half when two or more do.

    Uses two pins per PICAXE but only one wire between all of them. Something like ...

    Code:
    Do
      Do
        Input WANT_OUT
        Do
          ReadAdc ADC_IN, b0
        Loop Until b0 > $F0
        Low WANT_OUT
        Pause 1
        ReadAdc ADC_IN, b0
      Loop Until b0 > $70 And b0 < $90
      HI2C ...
    Loop

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