danners430
Member
Hey folks,
I'm designing an i2c network consisting exclusively of picaxe chips and a 24LC512 EEPROM. At one end, I've got a pair of chips communicating with a PC over serial, one an i2c slave handling serial comms to the PC, and the other an i2c master receiving data from the pc.
I know that the i2c protocol in theory protects the network from multiple masters transmitting at once. however, does the picaxe system also have this protection, where a master waits for the bus to be free before taking command and sending data?
If this doesn't work, my other option (much less preferred) is for the master chip to poll each of the chips one at a time to check for updates. How long would this take for, for example, 10 chips to have one bit parsed each?
Cheers folks
I'm designing an i2c network consisting exclusively of picaxe chips and a 24LC512 EEPROM. At one end, I've got a pair of chips communicating with a PC over serial, one an i2c slave handling serial comms to the PC, and the other an i2c master receiving data from the pc.
I know that the i2c protocol in theory protects the network from multiple masters transmitting at once. however, does the picaxe system also have this protection, where a master waits for the bus to be free before taking command and sending data?
If this doesn't work, my other option (much less preferred) is for the master chip to poll each of the chips one at a time to check for updates. How long would this take for, for example, 10 chips to have one bit parsed each?
Cheers folks