Haviing trouble simulating the srlatch

Buzby

Buzby

Senior Member
I'm trying to simulate the srlatch being set when c.1 ( the SRI pin ) goes high.

What am I doing wrong ?

Cheers,

Buzby

Code: 
[color=Navy]#picaxe [/color][color=Black]08M2[/color]
[color=Navy]#no_data[/color]
[color=Green]' PE 6.0.8.9[/color]


[color=Blue]high c.2 [/color][color=Green]' Make SRQ an output[/color]

[color=Blue]pause [/color][color=Navy]1000[/color]

[color=Green]' Set latch when SRI is 1
 [/color][color=Blue]srlatch [/color][color=Navy]%10001000[/color][color=Black], [/color][color=Navy]%10000000 [/color]


[color=Blue]do 
pause [/color][color=Navy]100 [/color][color=Green]' Put 'test for latch set' here [/color]
[color=Blue]loop [/color]
 
A

AllyCat

Senior Member
Hi,

Looks like a bug/oversight in PE6 (I've just tried 6.0.8.4) .

The code seems to simulate correctly in PE5.

Cheers, Alan.
 
Buzby

Buzby

Senior Member
I've got a new laptop, so I installed PE6 as my only PE.

Should have stuck with PE5 !.
 
Buzby

Buzby

Senior Member
Now I've just discovered that the srlatch clocked set/reset is not supported in PE5 or PE6 !.

I'll just have to build the hardware before I write the software.
 
A

AllyCat

Senior Member
Hi,

I'm not sure how "useful" is the clocked part of the SR-Latch, when using a PICaxe, because even its longest prescaler delay executes faster than a single PICaxe instruction.

How are you planning to use the SR-Latch? I have found the Latch(es) within the "Timer 1 Gate" hardware (which can be used totally independently of Timer 1) to have some useful features.

Cheers, Alan.
 
Buzby

Buzby

Senior Member
Hi Alan,

I must admit I wasn't planning on using the clocked set/reset, but it would be nice if it could be simulated.

I've not investigated the timer 1 gating, have you got any examples, or a link to the datasheet ?.

I'm trying to emulate something like the 'wake on interrupt' ( sleep 0 ) that the X2's can do, but on an 08M2, and active on both rising and falling edges.

Cheers,

Buzby
 
A

AllyCat

Senior Member
Hi Buzby,

I had been planning to post a Code Sniippett on the Timer1 Gate, but some time ago replied to another topic.

Maybe I will submit a detailed Code Snippett soon (to use either with or without Timer 1) , but for now the key diagrams (from the relevant base PIC data sheet) are in post #10 of the link above. Its particular strength is that the PICaxe Code can read the Latch status, but I'm not sure it would help your particular application.

Cheers, Alan.
 
Hemi345

Hemi345

Senior Member
Yeah, looks like a bug with the 08M2. The simulating almost the same code with the 20M2 works as expected:

Code: 
#picaxe 20M2
#no_data
' PE 6.0.8.9


high b.1 ' Make SRQ an output

pause 1000

' Set latch when SRI is 1
 srlatch %10001000, %10000000 
 pause 1000


do 
	pause 1000 ' Put 'test for latch set' here 
loop
 
Buzby

Buzby

Senior Member
Hi Alan,

That's clever use of the T1GCON register, but I don't think it will help me unless the gate is active during sleep, which I don't think it is.

Also, I maybe able to accommodate the fact that the srlatch is level triggered, not edge triggered, by judicious placement of the vibration switch I'm using to wake up.

Cheers,

Buzby
 
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